The present invention relates to an automatic power control system, and more particularly, to a power control system and related method for controlling an output power emitted from a laser diode (LD) for accessing/recording (i.e. reading from or writing to) an optical disc.
Generally speaking, in the field of optical storage media (e.g. DVD discs), an optical pick-up head unit (OPU) of an optical disc drive is utilized for outputting a laser light with an appropriate output power level from a laser diode (LD) onto an optical disc, for recording data onto the optical disc or reading data from the optical disc. Depending on different driving signals, the output power level emitted from the LD often alternates between an actual read power level, an actual write power level, and an actual peak power level (the actual peak power level is also called an actual overdrive (OD) power level) when the OPU accesses/records a recordable disc. Similarly, when the OPU accesses a rewritable disc, the output power level of the LD alternates frequently between an actual write power level (this is a highest laser power level), an actual erase power level, and an actual bias power level. Taking accessing of a recordable disc for example, in order to control the actual read/write power level at a target read/write power level when accessing data, an automatic power control (APC) loop is generally used to determine a read/write power control value by detecting the voltage level of a front photodiode output (FPDO) signal outputted from a front photodiode (FPD) in the OPU. The FPD is utilized for sensing the output power level emitted from the LD, and the voltage level of the induced FPDO signal corresponds to the output power level. Thus, for controlling the actual read/write power level, the APC loop is considered as a close loop control scheme. In addition, the APC loop adopts a sample-and-hold (S/H) scheme for sampling different voltage levels of the FPDO signal and holding the sampled results fed into the following power control stage.
Please refer to FIG. 44. FIG. 44 shows possible waveforms of a current signal ILD corresponding to the output power level emitted from the LD (when accessing/recording a recordable disc), an FPDO signal VFPDO, an S/H pulse signal P1, and an S/H pulse signal P2. As shown in FIG. 44, the S/H pulse signal P1 corresponds to the actual write power level and the S/H pulse signal P2 corresponds to the actual read power level. Since the current signal ILD corresponds to the driving current passing through the LD, it is possible that undesired overshots or undershots arise in the current signal ILD. Additionally, a frequency response of the FPD is usually not so fast such that the FPDO signal VFPDO may transit from one voltage level to another level smoothly and not so quickly (as shown in FIG. 44) instead of transiting between different levels sharply. As a result, some distortions are introduced. In this description, it is assumed that the S/H scheme do not affect the APC loop failing to control the actual read/write power level emitted from the LD at the target read/write power level. However, due to the distortions in the FPDO signal VFPDO, the APC loop cannot control the actual peak power level at a target peak power level correctly when utilizing the above-mentioned sample and hold scheme. This is due to two major reasons. One of the reasons is that a required settling time of the PFD is not fast enough. That is, the FPD senses the output power level emitted from the LD to generate the FPDO signal VFPDO not rapidly. Another reason is that the voltage level corresponding to the target peak power level in the FPDO signal VFPDO is usually affected by neighboring overshots or undershots. Thus, an S/H pulse signal corresponding to the actual peak power level outputted from the sample and hold scheme is usually erroneous. This problem will become more serious when the optical disc drive accesses/records a rewritable disc or when the recording speed of the optical disc drive is much higher.
Please refer to FIG. 45. FIG. 45 shows possible waveforms of a current signal ILD′, an FPDO signal VFPDO′, and an S/H pulse signal P3, where the current signal ILD′ corresponds to an output power level of the LD when accessing/recording a rewritable disc. The S/H pulse signal P3 corresponds to the actual erase power level. As mentioned above, although the FPDO signal VFPDO′ could be processed by an S/H unit to generate the S/H pulse signal P3 corresponding to the actual erase power level, it is very difficult to generate a correct S/H pulse signal corresponding to the actual write power level (i.e. the highest power level when accessing the rewritable disc) in a similar way. This is because the current signal ILD′ is usually shown in the form of multiple pulses. This means that the pulse widths of the multiple pulses are very short and so accurate identification that the voltage signal VFPDO′ transits from this level to another level cannot be ensured. Furthermore, the voltage signal VFPDO′ is also affected by the undesired overshots or undershots as described above. Therefore, when accessing/recording the rewritable disc, it is very probable to utilize an open loop control scheme instead of the APC loop (i.e. a close loop control scheme) for controlling the actual write power level emitted from the LD at the target write power level.
In general, for accessing/recording the above-mentioned recordable disc, there exist three conventional schemes for controlling the actual peak power level at the target peak power level. One of the conventional schemes adopts an open DAC scheme to generate a predetermined peak power control value. Once the temperature of the LD changes, however, a required driving current passing through the LD is also changed for outputting the same target peak power level. Thus, the actual peak power level emitted from the LD according to the predetermined peak power control value may be higher/lower than the original target peak power level. It is obvious that the open DAC scheme cannot control the actual peak power level emitted from the LD at the target peak power level effectively when a change of the temperature of the LD is taken into account.
Another conventional scheme uses a read power control value determined by the APC loop as an indicator to determine a peak power control value, for controlling the actual peak power level emitted from an LD at the target peak power level. This conventional scheme, however, has a major drawback. Please refer to FIG. 46. FIG. 46 is a diagram illustrating a characteristic curve CV of an LD. As shown in FIG. 46, the read, write, and peak power control values correspond to different amounts of current ΔIr, ΔIw, and ΔIpk respectively. If it is desired to emit a laser light with a target peak power level Ppk, the LD driver has to sum up the amounts of current Ith, ΔIr, ΔIw, and ΔIpk to derive a driving current Ipk for driving the LD to provide the target peak power level Ppk. Ith is meant to be a minimum required amount of current for conducting the LD. Similarly, if it is desired to emit a laser light with a target write power level Pw, the LD driver has to sum up the amounts of current Ith, ΔIr, and ΔIw to derive a driving current Iw for driving the LD to provide the target write power level Pw. It will be obvious that a slope (i.e. a gain of driving current vs. output power level) of the characteristic curve CV from zero to a target read power level Pr is greatly different from that of the characteristic curve CV from the target write power level Pw to the target peak power level Ppk. Therefore, the conventional scheme using the read power control value as the indicator to determine the peak power control value cannot correctly control the actual peak power level emitted from the LD at the target peak power level Ppk when the target read power level varies.
A final conventional scheme adopts the write power control value as an indicator to determine the peak power control value since a slope of the characteristic curve CV in FIG. 46 from the target read power level Pr to the target write power level Pw is almost identical to that of the characteristic curve CV from the target write power level Pw to the target peak power level Ppk. Please refer to FIG. 47. FIG. 47 is a schematic diagram of a conventional APC loop 2400 for controlling an output power level emitted from a laser diode D1 in an OPU 2405. As shown in FIG. 47, the APC loop 2400 comprises S/H units 2410 and 2415, analog-to-digital converters (ADCs) 2420 and 2425, a read power control circuit 2430, a write power control circuit 2435, digital-to-analog converters (DACs) 2440, 2445 and 2447, a digital gain amplifier GRATIO, and a plurality of adjustable gain amplifiers GR—ADJ, GW—ADJ, and GPK—ADJ. The OPU 2405 comprises a laser diode driver 2450, the laser diode D1, and a photo detector Q1 such as the aforementioned FPD. The laser diode driver 2450 comprises a plurality of gain amplifiers GR—LDD, GW—LDD, and GPK—LDD, a plurality of multiplexers MUX1, MUX2, and MUX3, and an analog adder Gsum. Usually, a signal path through the S/H unit 2410, the ADC 2420, the read power control circuit 2430, the DAC 2440, the adjustable gain amplifier GR—ADJ, and the gain amplifier GR—LDD is called a read channel; this signal path excluding the gain amplifier GR—LDD is a read channel power control path in the APC loop 2400. Similarly, a signal path through the S/H unit 2415, the ADC 2425, the write power control circuit 2435, the DAC 2445, the adjustable gain amplifier GW—ADJ, and the gain amplifier GW—LDD is called a write channel; the signal path excluding the gain amplifier GW—LDD is a write channel power control path in the APC loop 2400.
As described above, the S/H units 2410 and 2415 are configured to sample an FPDO signal VFPDO at different voltage levels and hold the sampled voltage levels for respective time periods before the FPDO signal VFPDO alternates from a current voltage level to another voltage level, for generating the S/H pulse signal P1 and the S/H pulse signal P2 of FIG. 44 respectively. Next, the ADCs 2420 and 2425 convert the S/H pulse signals P1 and P2 into digital values. The read power control circuit 2430 and write power control circuit 2435 then determine read and write power control values for controlling the output power level. The read and write power control values will be converted into driving signals Sr and Sw (e.g. driving currents or driving voltages) by the DACs 2440 and 2445, and the driving signals Sr and Sw will be transmitted into the OPU 2405 through the adjustable gain amplifiers GR—ADJ and GW—ADJ respectively. Continuously, if the multiplexer MUX1 or MUX2 is enabled by a control signal EN_R/EN_W, the gain amplifiers GR—LDD or GW—LDD then amplify the driving signals Sr/Sw for outputting driving signals Sr′/Sw′ to the analog adder Gsum.
For controlling the actual peak power level of the LD D1, as shown in FIG. 47, the determined write power control value will be taken as an indicator to be amplified by the digital gain amplifier GRATIO X times, for generating a peak power control value. This parameter X is meant to be a value, which is equal to (Ppk−Pw)/(Pw−Pr). The peak power control value is converted into a driving signal Spk by the DAC 2447. The driving signal Spk will then be amplified through the adjustable gain amplifier GPK—ADJ and the gain amplifier GPK—LDD, for outputting a driving signal Spk′ into the analog adder Gsum. To maintain the total gain of a peak channel equaling that of the write channel (where the peak channel in this conventional scheme is considered as a signal path through the DAC 2447, the adjustable gain amplifier GPK—ADJ, the gain amplifier GPK—LDD, and the analog adder Gsum) and to keep a ratio relation between the driving signals Sw′ and Spk′, it is necessary to consider gains of the gain amplifiers GW—LDD and GPK—LDD, the gain of the adjustable gain amplifier GW—ADJ, and a ratio relation between power differences ΔP and ΔP′ shown in FIG. 46 when setting the gain of the adjustable gain amplifier GPK—ADJ. Usually, the gain of the adjustable gain amplifier GPK—ADJ is designed in advance. Eventually, the analog adder Gsum can output a resultant driving signal for driving the LD D1 to provide the actual peak power level according to the driving signals Sr′, Sw′, and Spk′. Since the detailed operation of driving the laser diode is known to those skilled in this art, further description is omitted here for brevity's sake.
However, there exist some disadvantages. Since the write power control value depends on the target read power level Pr, the determined peak power control value will be different if the target read power level Pr is changed. For example, the target read power level Pr may be changed when the optical disc drive accesses/records data in different zones on a DVD-RAM disc, and therefore it may fail to directly use the determined write power control value as an indicator to generate a peak power control value for controlling the actual peak power level at the desired target peak power level. Even though the target read power level Pr is not changed, there is also some possibility that utilizing the write power control value as the indicator for generating the peak power control value to control the actual peak power level at the target peak power level may fail. This is because the required driving current passing through the LD D1 may be a little different when the optical disc drive accesses/records different discs belonging to the same type or the same kind of discs made up by different manufacturers. In other words, the write power control value also becomes a little different, so the changed write power control value after being multiplied by the above-mentioned parameter X may be not equal to a required peak power control value for achieving the target peak power level. In summary, this conventional scheme is still unable to control the actual peak power level at the target peak power level effectively.